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ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
15 years 2 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
ICCAD
1996
IEEE
89views Hardware» more  ICCAD 1996»
15 years 1 months ago
An algorithm for power estimation in switched-capacitor circuits
A number of low-power designs,such as those for mobile communicationequipment, containswitched-capacitorcircuits. In such designs it is important to be able to estimate the power ...
Chad Young, Giorgio Casinovi, Jonathan Fowler, Pau...
JCP
2008
324views more  JCP 2008»
14 years 9 months ago
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, A...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
15 years 6 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
IWANN
2005
Springer
15 years 3 months ago
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...
Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet