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DATE
2010
IEEE
134views Hardware» more  DATE 2010»
15 years 2 months ago
Simultaneous budget and buffer size computation for throughput-constrained task graphs
Abstract—Modern embedded multimedia systems process multiple concurrent streams of data processing jobs. Streams often have throughput requirements. These jobs are implemented on...
Maarten Wiggers, Marco Bekooij, Marc Geilen, Twan ...
MAM
2006
124views more  MAM 2006»
14 years 9 months ago
Design optimization and space minimization considering timing and code size via retiming and unfolding
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, M...
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
15 years 4 months ago
Gate sizing for large cell-based designs
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
Stephan Held
BIBE
2009
IEEE
126views Bioinformatics» more  BIBE 2009»
15 years 4 months ago
Mining Positional Association Super-Rules on Fixed-Size Protein Sequence Motifs
— Protein sequence motifs information is crucial to the analysis of biologically significant regions. The conserved regions have the potential to determine the role of the protei...
Bernard Chen, Sinan Kockara
ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
15 years 6 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang