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DAC
1995
ACM
15 years 1 months ago
Automatic Clock Abstraction from Sequential Circuits
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
Samir Jain, Randal E. Bryant, Alok Jain
WSC
2008
15 years 11 days ago
A new method for bottleneck detection
This paper presents a new method to identify and rank the bottlenecks in a manufacturing system. The proposed method is based on performance related data that are easy to capture,...
Sankar Sengupta, Kanchan Das, Robert P. VanTil
WSC
2008
15 years 11 days ago
Mathematical programming representations for state-dependent queues
Discrete-event dynamic systems with feedback, where the behavior of the system depends on the system state, are difficult to model due to the uncertainties and dependencies of sys...
Wai Kin Chan, Lee W. Schruben
ASPDAC
2005
ACM
130views Hardware» more  ASPDAC 2005»
15 years 12 hour ago
Stability analysis of active clock deskewing systems using a control theoretic approach
— In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is model...
Vinil Varghese, Tom Chen, Peter Young
MASCOTS
2004
14 years 11 months ago
A Hysteresis Model for Web/TCP Transfer Latency
This paper presents an accurate stochastic model for transfer latency of short-lived Web-like TCP flows with random packet losses. Our model characterizes a data transfer in alter...
Yujian Li, Carey L. Williamson