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CODES
2004
IEEE
15 years 3 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CC
2006
Springer
125views System Software» more  CC 2006»
15 years 3 months ago
Converting Intermediate Code to Assembly Code Using Declarative Machine Descriptions
Abstract. Writing an optimizing back end is expensive, in part because it requires mastery of both a target machine and a compiler's internals. We separate these concerns by i...
João Dias, Norman Ramsey
EUROMICRO
1998
IEEE
15 years 4 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
DAC
2003
ACM
15 years 5 months ago
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
CODES
2006
IEEE
15 years 5 months ago
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study
Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case stud...
Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo L...