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» Thermal modeling and management of DRAM memory systems
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ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 1 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
DAC
2006
ACM
14 years 11 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
ASPLOS
2011
ACM
14 years 1 months ago
MemScale: active low-power modes for main memory
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. Ho...
Qingyuan Deng, David Meisner, Luiz E. Ramos, Thoma...
WMPI
2004
ACM
15 years 2 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
DEBU
2010
113views more  DEBU 2010»
14 years 7 months ago
Storage Class Memory Aware Data Management
Storage Class Memory (SCM) is here to stay. It has characteristics that place it in a class apart both from main memory and hard disk drives. Software and systems, architectures a...
Bishwaranjan Bhattacharjee, Mustafa Canim, Christi...