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ENTCS
2006
163views more  ENTCS 2006»
14 years 12 months ago
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...
Frank K. Gürkaynak, Stephan Oetiker, Hubert K...
CODES
2006
IEEE
15 years 6 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
DATE
2008
IEEE
120views Hardware» more  DATE 2008»
15 years 6 months ago
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing...
Matthias May, Matthias Alles, Norbert Wehn
INFOCOM
2008
IEEE
15 years 6 months ago
Power Awareness in Network Design and Routing
Abstract—Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increa...
Joseph Chabarek, Joel Sommers, Paul Barford, Crist...
DSN
2011
IEEE
13 years 11 months ago
Cross-layer resilience using wearout aware design flow
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...
Bardia Zandian, Murali Annavaram