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ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
Dan Zhao, Unni Chandran, Hideo Fujiwara
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 3 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
ICWE
2010
Springer
14 years 10 months ago
Designing Context-Aware Interactions for Task-Based Applications
Since contextual information has potential to improve task-based applications, we provide an approach for integrating contextual information in task-based applications by consideri...
Pablo Muñoz, Pau Giner, Miriam Gil
LCTRTS
2001
Springer
15 years 4 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
DSD
2011
IEEE
194views Hardware» more  DSD 2011»
13 years 11 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...