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ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
15 years 11 months ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...
135
Voted
IEEEINTERACT
2003
IEEE
15 years 10 months ago
Compiler Support for Dynamic Speculative Pre-Execution
Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), whic...
Won Woo Ro, Jean-Luc Gaudiot
148
Voted
LCN
2000
IEEE
15 years 9 months ago
Intra-domain Bandwidth Management in Differentiated Services Network
In absence of any link layer traffic controls or priorityqueuing mechanism in LAN infrastructure (such as shared media LAN), Subnet Bandwidth Management based approach of managing...
Sanjay Jha, Mahbub Hassan, Priyadarsi Nanda, Nadee...
EDCC
1994
Springer
15 years 9 months ago
Hierarchical Checking of Multiprocessors Using Watchdog Processors
A new control flow checking scheme, based on assigned-signature checking by a watchdog processor, is presented. This scheme is suitable for a multitasking, multiprocessor environme...
István Majzik, András Pataricza, Mar...
ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
15 years 9 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi