165 search results - page 10 / 33 » Thread Cluster Memory Scheduling |
113
click to vote
ISPAN
1997
IEEE
15 years 3 months ago
1997
IEEE
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
IPPS
2009
IEEE
15 years 6 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
134
click to vote
SPAA
2012
ACM
13 years 2 months ago
2012
ACM
GPU-based heterogeneous clusters continue to draw attention from vendors and HPC users due to their high energy efficiency and much improved single-node computational performance...
85
Voted
SAC
2004
ACM
15 years 5 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
105
click to vote
ICPADS
2006
IEEE
15 years 5 months ago
2006
IEEE
Symmetric Multiprocessors (SMPs), combined with modern interconnection technologies are commonly used to build cost-effective compute clusters. However, contention among processor...