Sciweavers

165 search results - page 24 / 33
» Thread-Shared Software Code Caches
Sort
View
84
Voted
SIGSOFT
2007
ACM
16 years 12 days ago
Program comprehension as fact finding
Little is known about how developers think about design during code modification tasks or how experienced developers' design knowledge helps them work more effectively. We pe...
Thomas D. LaToza, David Garlan, James D. Herbsleb,...
97
Voted
CODES
2007
IEEE
15 years 6 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
CODES
2009
IEEE
15 years 6 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
113
Voted
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 3 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
LCTRTS
2000
Springer
15 years 3 months ago
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Matteo Corti, Roberto Brega, Thomas R. Gross