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» Three-dimensional integrated circuits
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167
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EVOW
2001
Springer
15 years 9 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
155
Voted
ICCAD
2003
IEEE
141views Hardware» more  ICCAD 2003»
15 years 10 months ago
An Enhanced Multilevel Algorithm for Circuit Placement
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shin...
FPGA
2003
ACM
156views FPGA» more  FPGA 2003»
15 years 10 months ago
Architectures and algorithms for synthesizable embedded programmable logic cores
As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programm...
Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton
148
Voted
ICCAD
2003
IEEE
118views Hardware» more  ICCAD 2003»
16 years 1 months ago
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
As the technology node progresses, thermal problems are becoming more prominent especially in the developing technology of three-dimensional (3D) integrated circuits. The thermal ...
Brent Goplen, Sachin S. Sapatnekar
ICCAD
2001
IEEE
104views Hardware» more  ICCAD 2001»
16 years 1 months ago
A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
Clayton B. McDonald, Randal E. Bryant