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124
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ICCAD
2010
IEEE
114views Hardware» more  ICCAD 2010»
15 years 3 months ago
On timing-independent false path identification
This paper is concerned with finding timing-independent false paths that cannot be sensitized under any signal arrival time condition in integrated circuits. Existing techniques r...
Feng Yuan, Qiang Xu
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 8 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
DAC
2004
ACM
16 years 6 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
INTEGRATION
2008
89views more  INTEGRATION 2008»
15 years 5 months ago
Exact ESCT minimization for functions of up to six input variables
In this paper an efficient algorithm for the synthesis and exact minimization of ESCT(Exclusive or Sum of Complex Terms) expressions for Boolean functions of at most six variables...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...
153
Voted
INTEGRATION
2008
101views more  INTEGRATION 2008»
15 years 5 months ago
An efficient terminal and model order reduction algorithm
The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the rece...
Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGau...