1476 search results - page 126 / 296 » Three-dimensional integrated circuits |
495
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DAC
2012
ACM
13 years 7 months ago
2012
ACM
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
220
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ISPD
2012
ACM
14 years 20 days ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
217
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DAC
2009
ACM
16 years 6 months ago
2009
ACM
Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and reliability of integrated...
149
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INTEGRATION
2007
15 years 5 months ago
2007
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
114
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DAC
2009
ACM
16 years 6 months ago
2009
ACM
With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the ther...