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NN
2006
Springer
15 years 5 months ago
Speed-accuracy trade-off in planned arm movements with delayed feedback
The Vector Integration to Endpoint (VITE) circuit describes a real-time neural network model simulating behavioral and neurobiological properties of planned arm and hand movements...
Dan Beamish, I. Scott MacKenzie, Jianhong Wu
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
15 years 3 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 11 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
IJCNN
2006
IEEE
15 years 11 months ago
In Situ Training of CMOL CrossNets
—— Hybrid semiconductor/nanodevice (“CMOL”) technology may allow the implementation of digital and mixed-signal integrated circuits, including artificial neural networks (...
Jung Hoon Lee, Konstantin Likharev
ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
15 years 10 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae