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SBCCI
2005
ACM
80views VLSI» more  SBCCI 2005»
15 years 10 months ago
On the design of very small transconductance OTAs with reduced input offset
In this paper it will be demonstrated, from the theory and measurements, that series-parallel (SP) mirrors allow building current copiers with copy factors of thousands, without d...
Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Mo...
INTEGRATION
2007
90views more  INTEGRATION 2007»
15 years 5 months ago
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear p...
Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong...
TODAES
2008
158views more  TODAES 2008»
15 years 5 months ago
Designing secure systems on reconfigurable hardware
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integ...
Ted Huffmire, Brett Brotherton, Nick Callegari, Jo...
ITC
2000
IEEE
123views Hardware» more  ITC 2000»
15 years 9 months ago
Combinational logic synthesis for diversity in duplex systems
We describe logic synthesis techniques for designing diverse implementations of combinational logic circuits in order to maximize the data integrity of diverse duplex systems in t...
Subhasish Mitra, Edward J. McCluskey
DAC
2007
ACM
16 years 6 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu