1476 search results - page 146 / 296 » Three-dimensional integrated circuits |
182
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
154
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
148
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
162
Voted
DAC
2006
ACM
16 years 7 months ago
2006
ACM
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
146
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...