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» Through Silicon Vias as Enablers for 3D Systems
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68
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CORR
2008
Springer
94views Education» more  CORR 2008»
15 years 25 days ago
Through Silicon Vias as Enablers for 3D Systems
This special session on 3D TSV
E. Jung, Andreas Ostmann, Peter Ramm, Jürgen ...
133
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NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
15 years 5 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
105
Voted
ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
15 years 9 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...
94
Voted
DATE
2009
IEEE
146views Hardware» more  DATE 2009»
15 years 7 months ago
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Abstract—Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption...
Marco Facchini, Trevor Carlson, Anselme Vignon, Ma...
136
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GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
14 years 10 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli