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92
Voted
ICCAD
2006
IEEE
15 years 9 months ago
2006
IEEE
— For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit char...
107
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RTCSA
2009
IEEE
15 years 7 months ago
2009
IEEE
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
95
Voted
ASPDAC
2009
ACM
15 years 7 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ISQED
2006
IEEE
15 years 6 months ago
2006
IEEE
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
109
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ISQED
2005
IEEE
15 years 6 months ago
2005
IEEE
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...