6111 search results - page 239 / 1223 » Time, Hardware, and Uniformity |
DATE
2003
IEEE
15 years 6 months ago
2003
IEEE
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
93
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DATE
2003
IEEE
15 years 6 months ago
2003
IEEE
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...
118
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DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
111
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ICCAD
2000
IEEE
15 years 5 months ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
ISSS
1996
IEEE
15 years 5 months ago
1996
IEEE
Traditionally, application specific computations have been focusing on numerically intensive data manipulation. Modern communications and DSP applications, such as WWW, interactiv...