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101
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ASPDAC
2009
ACM
127views Hardware» more  ASPDAC 2009»
15 years 7 months ago
Timing driven power gating in high-level synthesis
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
Shih-Hsu Huang, Chun-Hua Cheng
107
Voted
DATE
2008
IEEE
125views Hardware» more  DATE 2008»
15 years 7 months ago
Current source based standard cell model for accurate signal integrity and timing analysis
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
Amit Goel, Sarma B. K. Vrudhula
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
15 years 7 months ago
Logical Reliability of Interacting Real-Time Tasks
We propose the notion of logical reliability for real-time program tasks that interact through periodically updated program variables. We describe a reliability analysis that chec...
Krishnendu Chatterjee, Arkadeb Ghosal, Thomas A. H...
127
Voted
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
15 years 7 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
15 years 7 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...