6111 search results - page 248 / 1223 » Time, Hardware, and Uniformity |
88
Voted
ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
— Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the tim...
74
Voted
ISCAS
2003
IEEE
15 years 6 months ago
2003
IEEE
A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. I...
85
Voted
FSTTCS
2001
Springer
15 years 5 months ago
2001
Springer
Abstract. In [12] we started a research on a distributed-timed extension of Petri nets where time parameters are associated with tokens and arcs carry constraints that qualify the ...
124
click to vote
ICCD
2006
IEEE
15 years 9 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
99
Voted
ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
Modeling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. Rece...