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MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 11 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 11 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
166
Voted
IPPS
1997
IEEE
15 years 10 months ago
External Adjustment of Runtime Parameters in Time Warp Synchronized Parallel Simulators
Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
Radharamanan Radhakrishnan, Lantz Moore, Philip A....
170
Voted
GLOBECOM
2006
IEEE
16 years 6 days ago
Low-Complexity Adaptive High-Resolution Channel Prediction for OFDM Systems
Abstract— We propose a low-complexity adaptive highresolution channel prediction algorithm for pilot symbol assisted orthogonal frequency division multiplexing (OFDM) systems. Th...
Ian C. Wong, Brian L. Evans
IJVR
2008
106views more  IJVR 2008»
15 years 6 months ago
Improved View Frustum Culling Technique for Real-Time Virtual Heritage Application
Real-time virtual heritage application is normally executed with a high performance computer system. This is due to the complexity and highly computational cost which makes such sy...
Mohd Shahrizal Sunar, Abdullah Mohd Zin, Tengku M....