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IEEEPACT
2003
IEEE
15 years 3 months ago
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjee...
HPCA
2009
IEEE
15 years 10 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
CCGRID
2003
IEEE
15 years 3 months ago
Leveraging Non-Uniform Resources for Parallel Query Processing
Clusters are now composed of non-uniform nodes with different CPUs, disks or network cards so that customers can adapt the cluster configuration to the changing technologies and t...
Tobias Mayr, Philippe Bonnet, Johannes Gehrke, Pra...
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
15 years 4 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 3 months ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee