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ASAP
2007
IEEE
157views Hardware» more  ASAP 2007»
15 years 1 months ago
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations
Monte-Carlo simulations are used in many applications, such as option pricing and portfolio evaluation. Due to their high computational load and intrinsic parallelism, they are id...
David B. Thomas, Jacob A. Bower, Wayne Luk
ICDE
2010
IEEE
248views Database» more  ICDE 2010»
15 years 9 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
15 years 4 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
ASAP
2007
IEEE
95views Hardware» more  ASAP 2007»
15 years 4 months ago
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Sumit D. Mediratta, Jeffrey T. Draper
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
15 years 2 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu