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BMCBI
2005
246views more  BMCBI 2005»
14 years 9 months ago
ParPEST: a pipeline for EST data analysis based on parallel computing
Background: Expressed Sequence Tags (ESTs) are short and error-prone DNA sequences generated from the 5' and 3' ends of randomly selected cDNA clones. They provide an im...
Nunzio D'Agostino, Mario Aversano, Maria Luisa Chi...
IFIPPACT
1994
14 years 11 months ago
Microcode Generation for Flexible Parallel Target Architectures
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope ...
Rainer Leupers, Wolfgang Schenk, Peter Marwedel
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 2 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
RTAS
2008
IEEE
15 years 4 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
CAIP
1997
Springer
15 years 1 months ago
A New Hardware Structure for Implementation of Soft Morphological Filters
: A new hardware structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipeline...
Antonios Gasteratos, Ioannis Andreadis, Phillipos ...