Sciweavers

821 search results - page 21 / 165
» Time Dependent Processing in a Parallel Pipeline Architectur...
Sort
View
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 3 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
HPDC
2010
IEEE
14 years 10 months ago
A hybrid Markov chain model for workload on parallel computers
This paper proposes a comprehensive modeling architecture for workloads on parallel computers using Markov chains in combination with state dependent empirical distribution functi...
Anne Krampe, Joachim Lepping, Wiebke Sieben
ISCA
2007
IEEE
217views Hardware» more  ISCA 2007»
14 years 9 months ago
Parallel Processing of High-Dimensional Remote Sensing Images Using Cluster Computer Architectures
Hyperspectral sensors represent the most advanced instruments currently available for remote sensing of the Earth. The high spatial and spectral resolution of the images supplied ...
David Valencia, Antonio Plaza, Pablo Martín...
ACL
2001
14 years 11 months ago
Computational Properties of Environment-based Disambiguation
The standard pipeline approach to semantic processing, in which sentences are morphologically and syntactically resolved to a single tree before they are interpreted, is a poor fi...
William Schuler
PATMOS
2000
Springer
15 years 1 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...