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SIGPLAN
2008
14 years 9 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
IPPS
2002
IEEE
15 years 2 months ago
Real-Time Communication for Distributed Vision Processing Based on Imprecise Computation Model
In this paper we propose an efficient real-time communication mechanism for distributed vision processing. One of the biggest problems of distributed vision processing, as is the ...
Hiromasa Yoshimoto, Daisaku Arita, Rin-ichiro Tani...
SIGARCH
2010
89views more  SIGARCH 2010»
14 years 4 months ago
Efficient reconfigurable design for pricing asian options
Arithmetic Asian options are financial derivatives which have the feature of path-dependency: they depend on the entire price path of the underlying asset, rather than just the in...
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, ...
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 1 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
15 years 6 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks