821 search results - page 29 / 165 » Time Dependent Processing in a Parallel Pipeline Architectur... |
ISORC
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper presents an innovative hierarchical feedback adaptation method that efficiently controls the dynamic QoS behavior of real-time distributed data-flow applications, such ...
ICIP
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
WEA
2010
Springer
15 years 2 months ago
2010
Springer
Server based route planning in road networks is now powerful enough to find quickest paths in a matter of milliseconds, even if detailed information on time-dependent travel times...
106
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IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...
SPIESR
1998
14 years 11 months ago
1998
Abstract. Imaging applications such as filtering, image transforms and compression/decompression require vast amounts of computing power when applied to large data sets. These appl...