821 search results - page 47 / 165 » Time Dependent Processing in a Parallel Pipeline Architectur... |
ISPAN
1997
IEEE
15 years 2 months ago
1997
IEEE
Loop unrolling is one of the most promising parallelization techniques, because the nature of programs causes most of the processing time to be spent in their loops. Unrolling not...
HPCC
2009
Springer
15 years 2 months ago
2009
Springer
This paper studies a load scheduling strategy with nearoptimal processing time leveraging the computational characteristics of parallel DNA sequence alignment algorithms, specific...
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
ICCD
1997
IEEE
15 years 2 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In traditional parallel co-simulation approaches, the simulation speed is heavily limited by time synchronization overhead between simulators and idle time caused by data dependen...