Sciweavers

821 search results - page 54 / 165
» Time Dependent Processing in a Parallel Pipeline Architectur...
Sort
View
CCGRID
2009
IEEE
15 years 4 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
15 years 3 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
IEEEPACT
1998
IEEE
15 years 2 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
15 years 3 months ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti
ISCA
2009
IEEE
161views Hardware» more  ISCA 2009»
15 years 4 months ago
AnySP: anytime anywhere anyway signal processing
In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world—a device that we...
Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. ...