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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 3 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
74
Voted
EUROPAR
2007
Springer
15 years 1 months ago
An Evaluation of Parallelization Concepts for Baseline-Profile Compliant H.264/AVC Decoders
Due to the increasing performance requirements of decoding H.264/AVC in HDTV or larger resolutions, new approaches are necessary to enable real-time processing. According to the cu...
Klaus Schöffmann, Markus Fauster, Oliver Lamp...
73
Voted
IPPS
2005
IEEE
15 years 3 months ago
A Dependency Chain Clustered Microarchitecture
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
Satish Narayanasamy, Hong Wang 0003, Perry H. Wang...
IEEECGIV
2006
IEEE
15 years 3 months ago
Real-Time Tracking with Non-Rigid Geometric Templates Using the GPU
The tracking of features in real-time video streams forms the integral part of many important applications in human-computer interaction and computer vision. Unfortunately trackin...
Julius Fabian Ohmer, Frédéric Maire,...
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
15 years 2 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...