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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 3 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
HPCA
2004
IEEE
15 years 10 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel
AINA
2008
IEEE
15 years 4 months ago
Multi-Character Processor Array for Pattern Matching in Network Intrusion Detection System
—Network Intrusion Detection System (NIDS) is a system developed for identifying attacks by using a set of rules. NIDS is an efficient way to provide the security protection for ...
Yeim-Kuan Chang, Ming-Li Tsai, Yu-Ru Chung
ISSS
2002
IEEE
138views Hardware» more  ISSS 2002»
15 years 2 months ago
An Object-Oriented Design Process for System-on-Chip Using UML
The object-oriented design process has been a hot topic in software development since it will improve product quality and productivity significantly, which is also a major issue i...
Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya ...
ICPP
1992
IEEE
15 years 1 months ago
Adaptive Binary Sorting Schemes and Associated Interconnection Networks
Many routing problems in parallel processing, such as concentration and permutation problems, can be cast as sorting problems. In this paper, we consider the problem of sorting on ...
Minze V. Chien, A. Yavuz Oruç