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HPCA
2012
IEEE
13 years 5 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
PARCO
2003
14 years 11 months ago
SIMD design to solve partial differential equations
The relation between autonomous and communication phases determines the throughput of parallel structured information processing systems. Such a relation depends on the algorithm w...
R. W. Schulze
RE
2001
Springer
15 years 2 months ago
Evolving System Architecture to Meet Changing Business Goals: An Agent and Goal-Oriented Approach
Today's requirements engineering approaches focus on notation and techniques for modeling the intended functionality and qualities of a software system. Little attention has ...
Daniel Gross, Eric S. K. Yu
WWW
2010
ACM
15 years 4 months ago
Fast and parallel webpage layout
The web browser is a CPU-intensive program. Especially on mobile devices, webpages load too slowly, expending significant time in processing a document’s appearance. Due to powe...
Leo A. Meyerovich, Rastislav Bodík
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
15 years 4 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell