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EUROPAR
2007
Springer
15 years 1 months ago
Efficient Parallel Simulation of Large-Scale Neuronal Networks on Clusters of Multiprocessor Computers
To understand the principles of information processing in the brain, we depend on models with more than 105 neurons and 109 connections. These networks can be described as graphs o...
Hans E. Plesser, Jochen M. Eppler, Abigail Morriso...
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
15 years 6 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
IPPS
2006
IEEE
15 years 4 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
CSCW
2012
ACM
13 years 5 months ago
Towards self-optimizing collaborative systems
Two important performance metrics in collaborative systems are local and remote response times. Previous analytical and simulation work has shown that these response times depend ...
Sasa Junuzovic, Prasun Dewan
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 3 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin