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ASPLOS
2009
ACM
15 years 10 months ago
Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
Robert D. Cameron, Dan Lin
TVCG
2012
182views Hardware» more  TVCG 2012»
13 years 3 days ago
ISP: An Optimal Out-of-Core Image-Set Processing Streaming Architecture for Parallel Heterogeneous Systems
—Image population analysis is the class of statistical methods that plays a central role in understanding the development, evolution and disease of a population. However, these t...
Linh K. Ha, Jens Krüger, João Luiz Dih...
PRDC
2008
IEEE
15 years 4 months ago
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...
Viswanathan Subramanian, Arun K. Somani
ICRA
2002
IEEE
113views Robotics» more  ICRA 2002»
15 years 2 months ago
A Real-Time Visual Processing System using a General-Purpose Vision Chip
A real-time visual processing system using a generalpurpose vision chip, an image sensor in which photo detectors and processing elements are integrated, is described. In order to...
Shingo Kagami, Takashi Komuro, Idaku Ishii, Masato...
HPCA
1998
IEEE
15 years 2 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...