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ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
15 years 6 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
WSC
1998
14 years 11 months ago
Parallel Implementation of a Molecular Dynamics Simulation Program
We have taken a NIST molecular dynamics simulation program (md3), which was configured as a single sequential process running on a CRAY C90 vector supercomputer, and parallelized ...
Alan Mink, Christophe Bailly
FPL
2003
Springer
100views Hardware» more  FPL 2003»
15 years 3 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
HPCA
2009
IEEE
15 years 10 months ago
Elastic-buffer flow control for on-chip networks
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
George Michelogiannakis, James D. Balfour, William...
ATAL
2007
Springer
15 years 4 months ago
Distributed management of flexible times schedules
In this paper we consider the problem of managing and exploiting schedules in an uncertain and distributed environment. We assume a team of collaborative agents, each responsible ...
Stephen F. Smith, Anthony Gallagher, Terry L. Zimm...