652 search results - page 8 / 131 » Time Management in The High Level Architecture |
IPPS
2000
IEEE
15 years 1 months ago
2000
IEEE
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
SIGMOD
1991
ACM
15 years 1 months ago
1991
ACM
This paper presents an architecture for a persistent object store in which multi-level storage is explicitly included. Traditionally, DBMSs have assumed that all accessible data r...
WSC
2008
14 years 12 months ago
2008
Distributed simulation is desired in many industries to support analysis and decision making for complex and integrated problems. Interoperating commercial simulation packages usi...
79
Voted
ICCD
2005
IEEE
15 years 3 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...