658 search results - page 105 / 132 » Time Management in the DoD High Level Architecture |
DAGSTUHL
2006
14 years 11 months ago
2006
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
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ICAC
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper introduces a self-configuring architecture for scaling the database tier of dynamic content web servers. We use a unified approach to load and fault management based ...
VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
TASE
2008
IEEE
14 years 9 months ago
2008
IEEE
Lean buffering is the smallest buffer capacity, which is necessary and sufficient to ensure the desired production rate of a manufacturing system. Literature offers methods for des...