Sciweavers

658 search results - page 10 / 132
» Time Management in the DoD High Level Architecture
Sort
View
72
Voted
ICNS
2007
IEEE
15 years 3 months ago
Towards System-level Optimization for High Performance Unified Threat Management
To build holistic protection against complex and blended network threats, multiple security features need to be integrated into a unified security architecture, which requires in ...
Yaxuan Qi, Baohua Yang, Bo Xu, Jun Li
ASPLOS
1998
ACM
15 years 1 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
15 years 3 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
15 years 2 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
SIGOPSE
1998
ACM
15 years 1 months ago
MMLite: a highly componentized system architecture
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
Johannes Helander, Alessandro Forin