658 search results - page 11 / 132 » Time Management in the DoD High Level Architecture |
78
Voted
WSC
2008
14 years 12 months ago
2008
Distributed simulation is desired in many industries to support analysis and decision making for complex and integrated problems. Interoperating commercial simulation packages usi...
MSS
2003
IEEE
15 years 2 months ago
2003
IEEE
When data resides on tertiary storage, clustering is the key to achieving high retrieval performance. However, a straightforward approach to clustering massive amounts of data on ...
91
Voted
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
118
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ISCAPDCS
2004
14 years 11 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
80
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...