658 search results - page 27 / 132 » Time Management in the DoD High Level Architecture |
HICSS
2003
IEEE
15 years 2 months ago
2003
IEEE
The current IETF standardization work has highlighted the feasibility of providing the users with a QoS network architecture in the framework of Integrated Services over Different...
HICSS
1995
IEEE
15 years 1 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
97
Voted
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
66
Voted
CIKM
2008
Springer
14 years 11 months ago
2008
Springer
To find near-duplicate documents, fingerprint-based paradigms such as Broder's shingling and Charikar's simhash algorithms have been recognized as effective approaches a...
75
Voted
WSC
1997
14 years 11 months ago
1997
This paper discusses the design, development, and use of a performance monitoring tool for Distributed Interactive Simulations (DIS). A typical DIS environment consists of hundred...