658 search results - page 34 / 132 » Time Management in the DoD High Level Architecture |
ITC
2003
IEEE
15 years 2 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model...
ASYNC
1997
IEEE
15 years 1 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
69
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ICPP
2009
IEEE
15 years 4 months ago
2009
IEEE
—This paper reports a study of mapping the Finite Difference Time Domain (FDTD) application to the IBM Cyclops64 (C64) many-core chip architecture [1]. C64 is chosen for this stu...
117
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ISCI
2011
14 years 4 months ago
2011
It is well known that software maintenance and evolution are expensive activities, both in terms of invested time and money. Reverse engineering activities support the obtainment ...