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ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
15 years 4 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
PC
2007
161views Management» more  PC 2007»
14 years 9 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
98
Voted
EEE
2005
IEEE
15 years 3 months ago
SLA Representation, Management and Enforcement
As the IT industry is becoming more and more interested in service oriented business models and upcoming technologies like Web Services or Grid Computing, the need for automated c...
Adrian Paschke, Martin Bichler
ANCS
2011
ACM
13 years 9 months ago
A Scalability Study of Enterprise Network Architectures
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
Brent Stephens, Alan L. Cox, Scott Rixner, T. S. E...
114
Voted
DAC
2012
ACM
13 years 3 days ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...