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» Time Management in the DoD High Level Architecture
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173 views 158 votes 15 years 1 months ago  PE 2008»
The DiffServ architecture has been proposed as a scalable approach for upgrading the Internet, adding service differentiation functionalities. However, several aspects of this arc...
150 views 130 votes 16 years 1 months ago  VLSID 2008»
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
72 views 108 votes 15 years 5 months ago  SCCC 1999»
The recent studies in the distributed simulation area are focused in the High Level Architecture, defined by the DoD/USA, which proposes a standard environment to develop and run ...
142 views 130 votes 15 years 7 months ago  BERTINORO 2005»
Current computing environments are becoming increasingly complex in nature and exhibit unpredictable workloads. These environments create challenges to the design of systems that c...
97 views 101 votes 15 years 7 months ago  LSSC 2005»
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
112 views 123 votes 15 years 1 months ago  CORR 2006»
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
180 views 137 votes 15 years 6 months ago  WMPI 2004»
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
110 views 92 votes 15 years 1 months ago  MMS 2002»
This paper offers a high-level retrospective overview of the GOPI middleware platform which is the outcome of a three year project aimed at the development of generic, configurabl...
119 views 113 votes 15 years 7 months ago  ICPADS 2006»
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
160 views 119 votes 15 years 5 months ago  ISHPC 2000»
This paper describes transparent mechanisms for emulating some of the data distribution facilities offered by traditional data-parallel programming models, such as High Performance...