658 search results - page 47 / 132 » Time Management in the DoD High Level Architecture |
CORR
2006
Springer
14 years 9 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
103
click to vote
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
MMS
2002
14 years 9 months ago
2002
This paper offers a high-level retrospective overview of the GOPI middleware platform which is the outcome of a three year project aimed at the development of generic, configurabl...
ICPADS
2006
IEEE
15 years 3 months ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
ISHPC
2000
Springer
15 years 1 months ago
2000
Springer
This paper describes transparent mechanisms for emulating some of the data distribution facilities offered by traditional data-parallel programming models, such as High Performance...