658 search results - page 63 / 132 » Time Management in the DoD High Level Architecture |
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
15 years 4 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
MICRO
1998
IEEE
15 years 2 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
VLDB
1998
ACM
15 years 1 months ago
1998
ACM
Telecommunication networks process verylarge numbers of events in real time. In this environment, database applications demand both high throughput (at reasonable costs), and pred...
IPCCC
1999
IEEE
15 years 2 months ago
1999
IEEE
Many computer hardware and software architectures buffer data in memory to improve system performance. Volatile disk or file caches are sometimes used to delay the propagation of ...
CIKM
1999
Springer
15 years 2 months ago
1999
Springer
Large scale networked image retrieval systems face a number of problems that are not fully satis ed by current systems. On one hand, integrated solutions that store all image data...