658 search results - page 70 / 132 » Time Management in the DoD High Level Architecture |
WSC
2007
15 years 2 days ago
2007
Photolithography is generally regarded as the most constraining element in semiconductor manufacturing. This is primarily attributable to the high capital investment and extensive...
106
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DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
103
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FDL
2003
IEEE
15 years 3 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
ERSA
2004
14 years 11 months ago
2004
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...