658 search results - page 77 / 132 » Time Management in the DoD High Level Architecture |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Achieving high performance under a peak temperature limit is a first-order concern for VLSI designers. This paper presents a new model of a thermally-managed system, where a stoch...
SAMOS
2004
Springer
15 years 3 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
VLSID
2003
IEEE
15 years 10 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
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SIGMOD
2011
ACM
14 years 16 days ago
2011
ACM
Multitenant data infrastructures for large cloud platforms hosting hundreds of thousands of applications face the challenge of serving applications characterized by small data foo...