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» Time Management in the DoD High Level Architecture
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FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 1 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 3 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
IPPS
1996
IEEE
15 years 1 months ago
Implementing the Data Diffusion Machine Using Crossbar Routers
The Data Diffusion Machine is a scalable virtual shared memory architecture. A hierarchical network is used to ensure that all data can be located in a time bounded by O(logp), wh...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
DSRT
2002
IEEE
15 years 2 months ago
Bridging the HLA: Problems and Solutions
The High-Level Architecture (HLA) provides a common architecture for distributed modeling and simulation. In its original form, the HLA allows a number of simulations to be joined...
Jürgen Dingel, David Garlan, Craig Damon
86
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SEMWEB
2010
Springer
14 years 7 months ago
Compact Representation of Large RDF Data Sets for Publishing and Exchange
Abstract. Increasingly huge RDF data sets are being published on the Web. Currently, they use different syntaxes of RDF, contain high levels of redundancy and have a plain indivisi...
Javier D. Fernández, Miguel A. Martí...