658 search results - page 89 / 132 » Time Management in the DoD High Level Architecture |
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
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ISVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propos...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...